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職責(zé)描述: 1.RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips. 2.Design flow/methodology development and innovation for front-end design challenges. 3.Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips. 任職要求: 1.MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus. 2.New graduate or 3 years working experience. 3.Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows. 4.Familiar with tcl/Perl/Python program. 招聘人數(shù)：1人